1. Field of the Invention
The present invention relates to a technique for reducing the source current noise in a semiconductor integrated circuit and further relates to a decoupling circuit formed on a semiconductor chip as well as a technique effectively utilized for a method of determining an inductance of an inductor constituting the decoupling circuit.
2. Description of the Related Art
In a system using the semiconductor integrated circuit (hereinafter referred to as an LSI), a high frequency component of a change of current in the LSI generates an electromagnetic wave as well known in the art. The following techniques for suppression of electromagnetic radiation have been known. More particularly, the specification of JP-A-6-309050 discloses a semiconductor substrate 12 of the semiconductor device 10 having a constant current source element 24 interposed in a source voltage supply line 26 supplying a source voltage to the internal circuit 22 and a capacity means 30 connected to a ground voltage supply line 28 supplying a ground voltage to the internal circuit 22 and the source voltage supply line 26. Also, the specification of JP-A-8-288462 discloses a semiconductor integrated circuit device having a circuit grout 5, which includes a CPU 5, a bus 8, which is provided so as to surround the circuit group 5, and a terminal pad 9 which is arranged outside the bus 8, wherein the semiconductor integrated circuit device is also provided with constant potential lines 1a and 3a, which have a part routed to increase the parasitic inductance and reach the circuit group 5 from the constant potential terminal pads 2 and 4. Further, the specification of JP-A-2-25037 discloses that an inductance component 5 and a resistance component 5R are added to an LSI 1 for increasing voltage drop inside the LSI 1, wherein, since the voltage drop inside the LSI increases, the voltage drop outside the LSI is relatively decreased, reducing the noise level outside the LSI.
The technique for providing a decoupling circuit comprised of an inductor and a bypass capacitor on a printed circuit board faces a problem that the number of parts packaged in the printed circuit board increases to reduce the packaging density and increase costs of fabrication.
Further, the technique in which a constant current element is provided for a source voltage supply line on a semiconductor chip and a capacity means is connected between a source voltage line and a ground line has a disadvantage that the substantial source voltage level in the internal circuit is decreased by the constant current element on the source voltage supply line.
Furthermore, in the technique in which a fixed potential line, that is, source voltage line and a ground potential line are pulled about on a chip to increase a parasitic inductance component so as to suppress a change in source voltage, the ability of response to signals is degraded to make this technique undesirable. Also, in the technique of increasing inductance and resistance components by pulling about the source wiring in the LSI, the internal load or the source impedance increases, having a disadvantage that the change of source voltage in the internal circuit increases.
An object of the invention is to provide a semiconductor integrated circuit that can decrease the adverse influence upon the operation of the internal circuit and effectively prevent a high frequency component of source current change from generating an electromagnetic wave.
Another object of the invention is to provide a design technique that can easily determine an inductance of a source inductor and a source capacitance necessary for suppressing the source current noise to a desired value or less through simulation in designing the semiconductor integrated circuit.
The above and other objects and novel features of the present invention will become apparent from a description of the present specification taken in conjunction with the accompanying drawings.
Representative ones of inventions disclosed in the present application will be outlined as below.
Namely, according to one aspect of the present invention, in an LSI having a plurality of power supply pads and a plurality of ground potential pads, wiring conductors having impedances which are substantially equal to each other are provided between the plurality of power supply pads and a power supply line in the LSI.
More specifically, there are provided a plurality of first power supply pads, a plurality of second power supply pads, a first power supply line for supplying a first power supply voltage applied to the plurality of first power supply pads to an internal circuit, a second power supply line for supplying a second power supply voltage applied to the plurality of second power supply pads to the internal circuit, and a plurality of inductors each connected between each of the plurality of first power supply pads and the first power supply line and each being comprised of a wiring conductor in the form of a horse shoe, a U-shape, a frame shape, a spiral or a loop that makes a loop around the internal circuit by xc2xe turns or more so as to make the plurality of inductors may have mutually substantially equal impedances reaching nodes at which the internal circuit connects to the first power supply line.
With the above construction, the wiring conductors or inductors are respectively provided between the plurality of external power supply terminals and the power supply line in the semiconductor integrated circuit, whereby a change in source current passing through the inductors can be suppressed to ensure that propagation of the source current noise to the outside of the semiconductor integrated circuit can be prevented effectively to prevent the generation of an electromagnetic wave due to a high frequency component of the source current noise. Further, since any wiring conductors or inductors are not pulled about between the plurality of external ground terminals and the ground line in the LSI, the ability of response to signals is not degraded. In addition, the plurality of inductors respectively connected to the plurality of external power supply terminals can increase the source inductance in total. Further, the plurality of inductors connected in parallel can decrease the source impedance relative to the internal circuit.
Preferably, the wiring conductors constituting the plurality of inductors may each be formed so as to make a loop around the semiconductor chip and so as to be connected between the corresponding power supply pad and the first power supply line so that the direction of current flowing through each wiring conductor may be the same. This is because the parallel arrangement of a plurality of lines in which currents flow in opposite directions decreases the inductance. An inductor of a desired inductance can be formed without increasing the chip size to a substantially large extent in comparison with the conventional semiconductor integrated circuit devoid of inductor.
More preferably, each inductor may include a first wiring layer formed to make a loop around the semiconductor chip and a second wiring layer formed to overlap the first wiring layer, the start end of the first wiring layer may be connected to any one of the plurality of first power supply pads and the termination end of the first wiring layer may be connected to the start end of the second wiring layer, and the termination end of the second wiring layer is connected to the first power supply line. In other words, the inductor takes the form of a double coil comprised of mutually overlapping upper and lower two wiring layers. Through this, the inductance can be increased without increasing the occupation area of the internal circuit.
Preferably, each inductor may include a first wiring layer formed to make a loop around the semiconductor chip and a second wiring layer formed to overlap the first wiring layer, and the first wiring layer may be connected to the second wiring layer through a low impedance by way of through-holes formed in an insulating film for separating the first and second wiring layers. In other words, the inductor takes the form of a double coil comprised of mutually overlapping upper and lower two wiring layers that are connected by way of the through-holes formed in the insulating film. Through this, the resistance component of the inductor can be reduced without increasing the occupation area to sufficiently assure the source voltage of the internal circuit.
Preferably, the wiring layer constituting each inductor may be formed to make a loop around an area in which the internal circuit of the semiconductor chip is formed. With this construction, the wiring layer constituting the inductor can be formed of the wiring layer constituting the power supply line of the internal circuit and the signal line to ensure that the inductor can be formed without complicating the process.
Further, the wiring layer constituting each inductor may preferably be formed into a U-shape, a frame shape, a spiral or a loop shape that makes a loop around an area approximately equal to or slightly smaller than the occupation area of the internal circuit above the area in which the internal circuit of the semiconductor chip is formed. With this construction, the inductance can further be increased without increasing the occupation area.
Preferably, the wiring layer constituting each inductor may take a spiral form outside the area in which the internal circuit of the semiconductor chip is formed. Through this, the wiring layer constituting the inductor can be formed of the wiring layer constituting the power supply line of the internal circuit and the signal line and the inductor can be formed without complicating the process.
Further, the first and second power supply lines may preferably be formed in a mesh or net pattern over the whole area in which the internal circuit of the semiconductor chip is formed. With this construction, the resistance of the first and second power supply lines can be reduced and the source voltage of the internal circuit can be assured sufficiently.
Further, at a portion where the wiring layer constituting each inductor is parallel with the first power supply line, the wiring layer constituting the inductor or a wiring layer constituting the first power supply line may preferably be formed as one electrode of a capacitor and a conductive layer serving as the other electrode of the capacitor may be formed so as to oppose the one electrode through an insulating film, thus forming a bypass capacitor. With this construction, the bypass capacitor having a desired capacitance can be formed without increasing the chip size.
Further, a conductive layer formed separately from the conductive layers constituting the electrodes may preferably be provided to the insulating film between the one electrode and the other to decrease the distance between the one electrode and the other electrode. With this construction, a large capacitance can be obtained without increasing the area.
Further, a conductive layer formed separately from the conductive layers constituting the electrodes and formed with irregularities may preferably be provided for the insulating film between the one electrode and the other electrode so as to decreases the distance between the one electrode and the other electrode and increase the substantial opposing area. With this construction, a further larger capacitance can be obtained without increasing the area.
According to another aspect of the present invention, in determining an inductance Lchip of the source inductor and a source capacitance Cchip that are to be built in an LSI chip, when power supply wiring on the board and lead terminals and bonding wire of the LSI package have an inductance Lboard, the inductance of the source inductor and the source capacitance are so selected as to satisfy the following two inequalities:                                                                                                               (                                                                                            Imac                          ⁡                                                      (                            ω                            )                                                                                                    Imax                          ⁡                                                      (                            ω                            )                                                                                              ·                                              VCC0                        Vchip0                                                              )                                    2                                ⁢                                  (                                                                                    (                                                  ω                          ⁢                                                      xe2x80x83                                                    ⁢                          CchipRchip                                                )                                            2                                        +                    1                                    )                                            -                                                (                                      ω                    ⁢                                          xe2x80x83                                        ⁢                    CchipRchip                                    )                                2                                              +          1          -          Lboard                ≤        Lchip                            (        1        )                                                                    Imac              ⁡                              (                                  ω                  =                  0                                )                                      ·                          VCC0              Vchip0                                ⁢                                                                      Lboard                  +                  Lchip                                Cchip                                      ·                          exp              ⁡                              (                                                      -                                          G                                                                        4                          -                                                      G                            2                                                                                                                                ⁢                  a                  ⁢                                      xe2x80x83                                    ⁢                                      tan                    ⁡                                          (                                                                                                    (                                                          1                              -                                                              G                                2                                                                                      )                                                    ⁢                                                                                    4                              -                                                              G                                2                                                                                                                                                              2                          ⁢                          G                                                                    )                                                                      )                                              ⁢                      (                          2                                                4                  -                                      5                    ⁢                                          G                      2                                                        +                                      6                    ⁢                                          G                      4                                                        -                                      G                    6                                                                        )                          ≤                  Δ          ⁢                      xe2x80x83                    ⁢          V                                    (        2        )            
where Rchip represents source resistance, VCC represents generation voltage of the external voltage source, Vchip represents source voltage applied to the chip per se, Imac(xcfx89) represents the sum of currents flowing through all current sources in the chip, Ave(Imac(t)) represents time average of Imac, Imax(xcfx89) represents the maximum permissible value of source noise current at frequency (xcfx89), xcex94V represents a permissible value of voltage drop level of the chip and G in inequality (4) is a variable indicated by G=Rchip/{square root over ( )}{(Lboard+Lchip)/Cchip}.
The source noise current In is a current noise leaking from the LSI chip to the outside, that is, a noise as viewed when the power supply terminals of the chip are observed from the outside at the time that current is passed through the LSI chip. On the other hand, the permissible value AV of voltage drop level is a critical voltage drop level guaranteeing that the LSI does not operate erroneously by a voltage drop generated in the source voltage when the current Imac(xcfx89) is passed through the chip.
With the above construction, a method for determining easily the inductance of source inductor and the capacitance of the source capacitor necessary for suppressing the source current noise to a desired value or less through simulation can be provided.